1. Field of the Invention
The invention generally relates to reading data. Specifically, the invention relates to performing a read operation where data is received according to an external data strobe signal by an integrated circuit having an internal clock signal.
2. Description of the Related Art
Modern computer systems typically include a memory device which may be used to store data utilized by the computer system. Other devices in the computer system, for example, a computer processor or a memory controller, may access the data stored in the memory device and process the data or transfer the data to other devices in the computer system.
Data stored in the memory device is typically accessed by issuing read commands to the memory device. Each read command is usually issued via an interface of the memory device. In response to receiving a read command, the memory device may, at some time later, begin transmitting data requested by the read command via the interface of the memory device.
FIG. 1 is a block diagram depicting exemplary signals used to transmit data via the interface of a memory device. The depicted signals include the internal clock (CK, also referred to as the system clock) of an integrated circuit accessing the memory device, commands (COMMAND) issued by the integrated circuitry to the memory device, an external data strobe signal (referred to herein as DQS) generated using an external strobe signal and data bytes (DQ) presented by the memory device.
As depicted in FIG. 1, a read command (READ) may be issued to the memory device at time t0. Later, at time t1, the DQS signal may be lowered by the memory device, indicating that the memory device has received the read command. Data from the memory device is typically received beginning at some time later (e.g., t2) as specified by the column-address-strobe (CAS) latency (CL), for example, beginning in the last clock period of CL. When the data is presented on DQ, the DQS signal may be asserted, indicating that the data is ready to be read from DQ. In the depicted example, the data is received at time t3, half of the period tCK of a system clock cycle after t2, the beginning of the last clock period of CL.
However, the exact time at which DQS is asserted and the data is presented (as specified by the access time, tAC) with respect to the internal clock CK (e.g., the phase shift) may vary depending upon variances in the processes used to manufacture the memory device, the temperature of the memory device, the operating clock frequency of the memory device, the transmittal time between the memory device and the integrated circuit, and other variables in the computer system. Accordingly, the data access time during which the data may be received may vary, for example, from zero to as much as 1.5 times the clock period tCK of the internal clock CK.
Due to the variance in tAC and the transmittal time between the memory device and the integrated circuit, the internal clock signal CK may not be perfectly synchronized with the external data strobe signal DQS during the read operation. To successfully read the data, the integrated circuit typically attempts to synchronize the data being read via DQ/DQS with the internal clock CK. At the same time, in order to increase system performance, the operating frequency of the memory device may be increased, thereby decreasing the size of the data eye. As the size of the data window decreases, it may become more difficult for the integrated circuit to synchronize the data between the internal clock CK and the external data strobe signal DQS.
Accordingly, improved methods and apparatus are needed for synchronizing data received via an external strobe signal with an internal clock signal.